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Automatic custom instructions identification method for high level synthesis
XIAO Chenglong, LIN Jun, WANG Shanshan, WANG Ning
Journal of Computer Applications
2018, 38 (7):
2024-2031.
DOI: 10.11772/j.issn.1001-9081.2018010062
Aiming at the problems that it is difficult to improve performance and reduce power consumption in the process of High Level Synthesis (HLS), an automatic custom instructions identification method for high level synthesis was proposed. The enumeration and selection of custom instructions were implemented before high level synthesis, so as to provide a universal automatic custom instructions identification method for high level synthesis. Firstly, the high level source code was transformed into a Control Data Flow Graph (CDFG), and the source code was preprocessed. Secondly, a subgraph enumeration algorithm was used to enumerate all the connected convex subgraphs in a bottom-up manner from the Data Flow Graph (DFG) based on control data flow graph, which effectively improved the user's ability to flexibly modify the constraints. Then, considering the area, performance and code size, the subgraph selection algorithms were used to select partial optimal subgraphs as the final custom instructions. Finally, a new code was regenerated by incorporating the selected custom instructions as the input of high level synthesis. Compared with the traditional high level synthesis, the pattern selection based on frequency of occurrence reduced the area by an average of 19.1%. Meanwhile, the subgraph selection based on critical paths reduced the latency by an average of 22.3%. In addition, compared with Transitive Digraph (TD) algorithm, the enumeration efficiency of the proposed algorithm was increased by an average of 70.8%. The experimental results show that the automatic custom instructions identification method can significantly improve performance and reduce area and code size for high level synthesis in circuit design.
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